The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
As the semiconductor device sizes continue to shrink, for example below 20 nanometer (nm) nodes, negative tone development (NTD) processes may be needed to achieve the small device sizes. However, even NTD processes may still have drawbacks related to depth of focus (DOF), line width roughness (LWR), or scum. These issues degrade lithography performance and may lead to decreased yield or even device failures.
Therefore, while existing NTD processes have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.